Blueprint · circuit executor

Qwen3.8-27B-NVFP4

qwen3.8-27b-nvfp4-unsloth on NVIDIA GB10 (DGX Spark)

Dense hybrid: 3 GatedDeltaNet layers then 1 gated full-attention layer, SwiGLU FFN, MTP draft head

Preview — unsigned Coming soon: no signed .kbp exists for a preview.

Hardware: GB10NVIDIA GB10 (DGX Spark) · sm_121f
Layers: 6416 full attention / 48 linear attention
Kernels: 1913 modules · 13 families
Decode step: 755launches · 757 kernel groups
Graph: 1,060nodes · 1,411 edges
Context: 32kmax sequence length

Architecture

Plan arm decode n=1 · digest 152bf34432db · 4 templates over 64 layers. Drag to orbit (pan in 2D); zoom with the wheel, a pinch or the zoom buttons; select a node for its kernel and numerics.

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Templates and layer sequence

Layer templates
Template	Blocks	Nodes	Edges	Fused groups	Used by
`embed`	`embed`	1	0	0	once
`attn+dense_ffn`	`attn` + `dense_ffn`	18	23	3	16 layers
`gdn+dense_ffn`	`gdn` + `dense_ffn`	16	19	3	48 layers
`head`	`head`	3	2	0	once

Kernels

19 entries in 13 modules, 13 kernel families (0 outside any family). The decode step launches 755 kernels in 755 device groups, plus 2 on the host.

Kernels the plan launches
Kernel (module::func)	Family	Compute unit	Groups
`causal_conv1d::causal_conv1d_update_l2norm_f32`	`causal_conv1d_l2norm`	`cuda_core`	48
`gated_delta_rule::gated_delta_rule_decode_f32`	`gdn_recurrence`	`cuda_core`	48
`gemv::dense_gemv_bf16`	`dense_bf16`	`cuda_core`	1
`moe_silu_mul::moe_silu_mul`	`silu_mul`	`memory`	64
`norm::gated_rms_norm_f32_input`	`gated_rms_norm`	`memory`	48
`norm::residual_add_rms_norm`	`rms_norm`	`memory`	64
`norm::rms_norm`	`rms_norm`	`memory`	33
`norm::rms_norm_residual`	`rms_norm`	`memory`	1
`paged_decode::paged_decode_attn`	`paged_decode_attn`	`cuda_core`	16
`reshape_and_cache::reshape_and_cache_flash`	`kv_write`	`memory`	16
`residual_add::bf16_residual_add`	`residual_add`	`memory`	1
`residual_add::sigmoid_gate_mul`	`sigmoid_gate_mul`	`memory`	16
`residual_add_rms_norm_exact::residual_add_rms_norm_exact`	`rms_norm`	`memory`	63
`rope_mrope_interleaved::rope_forward_mrope_interleaved`	`rope`	`memory`	16
`ssm_preprocess::dense_gemv_ba_gates`	`gdn_ba_gates_gemv`	`cuda_core`	48
`w4a16_gemv::w4a16_gemv_qg`	`w4a16_gemv`	`cuda_core`	16
`w4a16_gemv::w4a16_gemv_sw`	`w4a16_gemv`	`cuda_core`	176
`w4a16_gemv_fused::w4a16_gemv_dual`	`w4a16_gemv`	`cuda_core`	16
`w4a16_gemv_fused::w4a16_gemv_dual_sw`	`w4a16_gemv`	`cuda_core`	64

Precision

Tier recipe, table unsloth--Qwen3.8-27B-NVFP4 (ab75a565830e). KV cache bf16. Formats are the plan's: weight as stored, activation as the kernel reads it.

Weighted nodes

Weight and activation formats of the weighted nodes
Weight	Activation	Nodes
`nvfp4/g16`	`bf16`	288
`bf16`	`bf16`	49

Node outputs

Output formats of every node
Output format	Nodes
`bf16`	723
`f32`	192
`f32,f32`	48
`bf16,bf16`	32
`i32`	1

Plan arms

Every (mode, rows) arm the instance lists, fused by the planner; a loader with the same rule set re-plans each one and must reproduce its digest.

Plan arms
Mode	Rows	Groups	Launches	Fused edges	Materialized	Digest
`decode`	1	757	755	112	964	`152bf34432db`
`multi_seq`	2	757	755	112	964	`9fb0c4f697d1`route `gdn_state_slots_fragmented`: 757 groups, `e87bb042c8bf`
`multi_seq`	4	789	851	96	980	`01dff49ff8d6`route `gdn_state_slots_fragmented`: 789 groups, `5afa8892061f`
`multi_seq`	8	741	947	144	932	`78c60d0a8c47`route `gdn_state_slots_fragmented`: 741 groups, `2c1ba1b63d58`
`multi_seq`	12	725	979	160	916	`e02afa684597`route `gdn_state_slots_fragmented`: 725 groups, `d95cebf7bc0f`
`multi_seq`	16	725	979	160	916	`a96f6d50c7d3`route `gdn_state_slots_fragmented`: 725 groups, `5c123ff716f9`
`multi_seq`	24	725	979	160	916	`d7f07e3243d6`route `gdn_state_slots_fragmented`: 725 groups, `5ff1b0a671f0`
`multi_seq`	32	725	979	160	916	`182c58bea573`route `gdn_state_slots_fragmented`: 725 groups, `61d2f275ba7d`
`multi_seq`	48	725	979	160	916	`2f95abc59e91`route `gdn_state_slots_fragmented`: 725 groups, `322bb21ce2ca`
`multi_seq`	64	725	979	160	916	`41567728b92a`route `gdn_state_slots_fragmented`: 725 groups, `c2dcb6435ff6`
`multi_seq`	96	725	915	160	916	`076627915154`route `gdn_state_slots_fragmented`: 725 groups, `fb2fe504950f`
`multi_seq`	128	725	915	160	916	`b3c748703a5f`route `gdn_state_slots_fragmented`: 725 groups, `51314a7cf394`
`verify`	2	757	805	112	964	`bd01c3cf093e`
`verify`	3	757	854	112	964	`05cc3bb74500`
`verify`	4	789	999	96	980	`40514213278c`
`draft`	1	25	25	0	28	`b05422cfb078`
`draft`	2	25	26	0	28	`394761a68e5e`
`draft`	5	25	29	0	28	`93f0efa18d61`
`draft`	8	25	32	0	28	`0eac917b9ae8`
`draft`	9	25	33	0	28	`662d638ee808`
`draft`	16	25	40	0	28	`875fa7469f53`
`draft`	17	25	41	0	28	`f4342389f11e`
`draft`	32	25	56	0	28	`765f4169ad0f`

Performance

No measured record attached

A number appears here only with the fingerprint of the record it comes from. No benchmark record for this blueprint's serve is in the store yet.

Signature and sizes

Unverified

This is a preview: no blueprint body has been built or signed, so there is nothing to verify. Its id is a preview: hash of the slug and the plan digest, never a body hash.

Suite: mldsa65+ed25519 (ML-DSA-65 and Ed25519; both must verify)
Key id: none
Trust anchor: none
Blueprint id: 5fb02e4b02b2
Lineage: 299ae55c7818 · revision 0

Body: not built
Lite file: not built
Full file: not built
Download: No .kbp file exists for a preview: blueprint builds and signing are not available yet.

Provenance

Exported by preview: tools/preview/kbp_preview.py over `met circuit plan` (not `met blueprint export`). Engine tree c5b9a80e635d, planner binary f4735654ee1d (built from c5b9a80e635d). Target gb10/qwen3.8-27b/nvfp4.

Planner settings

activation_quantization=adaptivedecode_split_silu=ongemv_sw=onkv_cache_dtype=bf16lm_head_dtype=bf16rms_norm_act_quant=offrow_tiers=by_rowsssm_ba_gates_hopper=onssm_batched_recurrent=onssm_h_dtype=f32w4a16_tc=on

The 23 planner commands

met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode decode --rows 1
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode multi_seq --rows 2
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode multi_seq --rows 4
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode multi_seq --rows 8
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode multi_seq --rows 12
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode multi_seq --rows 16
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode multi_seq --rows 24
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode multi_seq --rows 32
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode multi_seq --rows 48
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode multi_seq --rows 64
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode multi_seq --rows 96
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode multi_seq --rows 128
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode verify --rows 2
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode verify --rows 3
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode verify --rows 4
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode draft --rows 1
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode draft --rows 2
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode draft --rows 5
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode draft --rows 8
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode draft --rows 9
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode draft --rows 16
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode draft --rows 17
met circuit plan --root <tree> --checkpoint qwen3.8/qwen3.8-27b-nvfp4-unsloth --hardware gb10 --precision recipe --format plan --mode draft --rows 32

The 8 engine files read, with their SHA-256

Engine files read
File	SHA-256
`kernels/circuits/INSTANCES.toml`	`31418b33cf20`
`recipes/qwen3.8/qwen3.8-27b-nvfp4-unsloth.yaml`	`d740dae13f46`
`kernels/gb10/HARDWARE.toml`	`24901961e415`
`kernels/DEVICES.toml`	`256d85840f0e`
`kernels/circuits/qwen3_5.toml`	`64a2d3106d56`
`kernels/circuits/blocks/qwen3_hybrid.toml`	`cfe66fc69723`
`kernels/gb10/common/KERNEL_FAMILIES.toml`	`4b8e793753ee`
`kernels/circuits/checkpoints/unsloth--Qwen3.8-27B-NVFP4.toml`	`ab75a565830e`

The documents themselves: card.json (kbp-card/v1) and graph.json (kbp-graph/v1).